![]() ![]() This is to ensure that the simulator and synthesis tool agree with each other, avoiding critical bugs that can only been discovered through gate-level simulation or even post-silicon tests. A rule of thumb is that any signals in your synthesizable design should be declared as logic (a few exceptions apply, which will be discussed). It can either represent a combinational signal or a sequential signal, since the downstream tools such simulator and synthesis tools will determine whether to instantiate a flip-flop based on the usage. Logic is the most commonly used basic data types in SystemVerilog. This can be useful when dealing with x-prorogation.ĭata types that only use 0 or 1 have 2-state values. Any 4-state value OR with 1 is 1, any 4-state value AND with 0 is 0, and any 4-state value XOR with x is x. Notice that the truth table for 4-state values are slightly different than the normal 2-state values. Keep in mind that x can propagate through your circuit if not taken care of, since any logic operation on unknown values results in unknown values. Any signal coming out from the shut-down region will be x. Another common scenario is low-power designs where some part of circuit is “shut-down”, i.e. no supply voltage. One common situation for x to appear in simulation is usage of uninitialized memory cells. Unknown value x means the system is able to determine the value, which may happen in various condition. It commonly appears in designs where a pin used as a bi-directional bus, e.g. tri-state. High-impedance value z typically implies a physically disconnected state, i.e. an infinitely high resistance. ![]() Values 0 and 1 serve the same purpose as in languages such as C/C++, but x and z are hardware specific. 1: represents a logic one or true condition. ![]()
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